Professional Background

-      2001-2009 : Gemplus / Gemalto Securiy Labs as security research engineer.

-      2009-2016 : CEA Tech as researcher in security of embedded systems in the SAS laboratory (joint research laboratory between the Mines St Etienne and the CEA Tech).

-      2016-2018 : CEA Leti as senior scientific advisor in the Division for the security of embedded systems and connected objects.

-      2019-now : CEA Leti as head of the embedded systems’ securing laboratory.

 

Academic Background

-      Electrical engineering degree from the Ecole Supérieure d'Électricité (SUPÉLEC - France).

-      Masters of Science in Electrical & Computer Engineering from the Georgia Institute of Technology (Atlanta - USA) with a major in signal processing and security and a minor in security policies and international affairs from the Sam Nunn School of International Affairs.

-      PhD in Computer Science from the University of Cambridge (Trinity Hall) on data parallel architectures for secure implementation of cryptography in embedded systems (PhD).

-      “Habilitation à Diriger des Recherches” (HDR) in computer science from the Université de Limoges.

 

 

 

 

 

 

Research

 
[J] Journal Paper, [BC] Book Chapter, [PAT] Published or Delivered Patent, [CP] Conference Paper (peer reviewed), [IT] Invited talk/paper.
 

Cryptography (Key words: Pairing based Cryptography, Light Weight Cryptography, AES, RSA, ECC, side channels, cache attacks, fault attacks…)

 

[CP] “Template Attacks against ECC: practical implementation against Curve25519” by Antoine Loiseau, Maxime Lecomte and Jacques J.A. Fournier, to appear in the proceedings of HOST 2020.

 

[J] “Improving side-channel attacks against pairing-based cryptography” by Damien Jauvart, Nadia El Mrabet, Jacques J.A. Fournier and Louis Goubin, in the Journal of Cryptographic Engineering (JCEN), pp1-16, January 2019.

 

[CP] “Practical Algebraic Side-Channel Attacks on ACORN” by Alexandre Adomnicai, Laurent Masson & Jacques Fournier, to appear in the proceedings of the 21st International Conference on Information Security and Cryptology (ICISC 2018), Seoul, Korea, November 2018.

 

[CP] “Masking the Lightweight Authenticated Ciphers ACORN and Ascon in Software” by Alexandre Adomnicai, Laurent Masson & Jacques Fournier, in the proceedings of BalkanCryptSec 2018, Romania, September 2018.

 

[PAT] “Cryptographic Method on binary Edwards elliptic curves” by Antoine Loiseau and Jacques J.A. Fournier, publication number 20190081786, filed in September 2018.

 

[CP] “Binary Edwards Curves for intrinsically secure ECC implementations for the IoT” by Antoine Loiseau and Jacques J.A. Fournier, in the proceedings of the 15th International Conference on Security and Cryptography (SECRYPT 2018), Springer-Verlag, Porto, July 2018.

 

[CP] “Thwarting Fault Attacks against Lightweight Cryptography using SIMD Instructions” Benjamin Lac, Anne Canteaut, Jacques Fournier and Renaud Sirdey, in the proceedings of the IEEE ISCAS 2018, Florence (Italy), May 2018.

 

[CP] “Bricklayer Attack: A Side-Channel Analysis on the ChaCha Quarter Round” by Alexandre Adomnicai, Laurent Masson & Jacques Fournier, in the proceedings of the INDOCRYPT 2017, Springer-Verlag, Chennai, November 2017.

 

[CP] “First Practical Side-Channel Attack to Defeat Point Randomization in Secure Implementations of Pairing-Based Cryptography” by Damien Jauvart, Jacques J.A. Fournier and Louis Goubin, in the proceedings of the 14th International Conference on Security and Cryptography (SECRYPT 2017), Springer-Verlag, Madrid, July 2017.

 

[CP] “DFA on LS-Designs with a Practical Implementation on SCREAM” by Benjamin Lac, Anne Canteaut, Jacques Fournier and Renaud Sirdey, in the proceedings of COSADE 2017, Springer-Verlag, Paris, April 2017.

 

[CP] “On the importance of considering physical attacks when implementing lightweight cryptography” by Alexandre Adomnicai, Benjamin Lac, Anne Canteaut, Laurent Masson, Renaud Sirdey, Assia Tria and Jacques J.A. Fournier, NIST Workshop on Light Weight Cryptography, October 2016.

 

[CP] “A First DFA on PRIDE: from Theory to Practice” by Benjamin Lac, Marc Beunardeau, Anne Canteaut, Jacques Fournier and Renaud Sirdey, in the proceedings of the 11th International Conference on Risks and Security of Internet and Systems (CRISIS 2016), Springer-Verlag, Roscoff, September 2016.

 

[CP] “Improving Side-Channel Attacks against Pairing-Based Cryptography” by Damien Jauvart, Jacques Fournier, Nadia El Mrabet and Louis Goubin, in the proceedings of the 11th International Conference on Risks and Security of Internet and Systems (CRISIS 2016), Springer-Verlag, Roscoff, September 2016.

 

[IT] “How careful should we be when implementing cryptography for software update mechanisms in the IoT?” by Alexandre Adomnicai, Jacques Fournier, Laurent Masson & Assia Tria, in the Internet of Things Software Update Workshop (IoTSU), June 2016.

 

[J] “A survey of Fault Attacks in Pairing Based Cryptography” by Nadia El Mrabet, Jacques J.A. Fournier, Louis Goubin & Ronan Lashermes, in the Special Issue of “Cryptography and Communication” on “Discrete Structures for side channel attacks and countermeasures”, Volume 7, Issue 1, pp 185-205, Springer, March 2015.

 

[CP] “Practical validation of several fault attacks against the Miller algorithm” by Ronan Lashermes, Marie Paindavoine, Nadia El Mrabet, Jacques J.A. Fournier & Louis Goubin, in the Proceedings of FDTC 2014, Busan, September 2014.

 

[CP] Inverting the final exponentiation of Tate pairings on ordinary elliptic curves using faults by R. Lashermes, J. Fournier & L. Goubin, in the proceedings of the CHES 2013, LNCS, Springer-Verlag, September 2013.

 

[CP] “A DFA on AES based on the entropy of error distributions” by R. Lashermes, G. Reymond, J-M. Dutertre, J. Fournier, B. Robisson & A. Tria, in the proceedings of the 9th international workshop on Faults Diagnosis and Tolerance in Cryptography (FDTC 2012), pp 34-43, IEEE Computer society publisher, September 2012.

 

[CP] ElectroMagnetic Analysis (EMA) of software AES on Java mobile phones” by D. Aboulkassimi, L. Freund, J. Fournier, M. Agoyan, B. Robisson & A. Tria, in the proceedings of the IEEE International Workshop on Information Forensics and Security (WIFS’11), November 2011.

 

[J]Design & characterisation of an AES chip embedding countermeasures by M. Agoyan, S. Bouquet, J-M. Dutertre, J. Fournier, J-B. Rigaud, B. Robisson & A. Tria, in the International Journal of Intelligent Engineering Informatics (IJIEI) – Special Issue on ‘Communication and Security Systems’, vol. 1, n° 3/4, pp 328-347, November 2011.

 

[CP] Design of a duplicated fault-detecting AES chip and yet using clock set-up time violations to extract 13 out of 16 bytes of the secret key by M. Agoyan, S. Bouquet, M. Doulcier-Verdier, J-M. Dutertre, J. Fournier, J-B. Rigaud, B. Robisson & A. Tria, in the Proceedings of Smart Systems Integration 2011 (SSI 2011), March 2011.

 

[CP] “Cache Based Power Analysis Attacks on AES” by Jacques Fournier & Michael Tunstall in the LNCS Proceedings of the 11th Australasian Conference on Information Security and Privacy (ACISP’06), Melbourne Australia, July 2006.

 

[PAT] “Procédé pour contrer les attaques de type ‘canaux cachés’ lors de la manipulation de données” de B. Chevallier-Mames, M. Ciet, J. Fournier & K. Villegas. Published Applications: FR0511268 / EP1949292 / WO2007051770, November 2005.

 

Security of Integrated Circuits (Key words: Reverse engineering, laser faults, EMA, Asynchronous circuits…)

 

[CP] Backside Shield against Physical Attacks for Secure ICs” by S. Borel, E. Deschaseaux, J. Charbonnier, Ph. Médina, S. Anceau, J. Clédière, R. Wacquez, J. Fournier, E. Jalaguier, Ch. Plantier and G. Simon., in the Proceedings of the 13th International Conference and Exhibition on DEVICE PACKAGING (DPC2017), Arizona, March, 2017.

 

[J] "Combining image processing and laser fault injections for characterizing a hardware AES" by Franck Courbon, Jacques J.A. Fournier, Philippe Loubet-Moundi, & Assia Tria, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), special issue on Hardware Security and Trust, Vol. 34, issue 6, June 2015.

 

[CP] Increasing the efficiency of laser fault injections using fast gate level reverse engineering” by Franck Courbon, Philippe Loubet-Moundi, Jacques J.A. Fournier & Assia Tria, in the Proceedings of HOST 2014, Washington DC, May 2014.

 

[CP] Adjusting laser injections for fully controlled faults” by Franck Courbon, Philippe Loubet-Moundi, Jacques Fournier & Assia Tria, in the Proceedings of COSADE 2014, Paris, April 2014.

 

[J] “EMA as a physical method for extracting secret data from mobile phones” by D. Aboulkassimi, J. Fournier, L. Freund, B. Robisson & A. Tria, in the International Journal of Computer Science and Applications (IJCSA) 2013, Vol. 2, N° 1, pp 16-25, Science and Engineering Publishing Company, USA, 2013.

 

[J] “Security characterisation of a hardened AES cryptosystem using a laser” by C. Roscian, F. Praden, J-M. Dutertre, J. Fournier & A. Tria, in the journal “Technical Sciences”, University of Warmia and Mazury in Olsztyn, pp 139-154, UWM publisher, Poland, September 2012.

 

[BC] “EM probes characterisation for security analysis” by B. Mounier, A-L. Ribotta, J. Fournier, M. Agoyan & A. Tria, in ‘Cryptography and Security: From Theory to Applications’, Quisquater Festschrift, pp 248-264, D. Naccache editor, Springer LNCS 6805, March 2012.

 

[CP] “Review of fault injection mechanisms and consequences on countermeasures’ design” by J-M. Dutertre, J.J-A. Fournier, A-P. Mirbaha, D. Naccache, J-B. Rigaud, B. Robisson & A. Tria, in the Proceedings of Design & Technology of Integrated Systems 2011 (DTIS 2011), April 2011.

 

[CP] “Memory address scrambling revealed using fault attacks” by Jacques J.A. Fournier & Philippe Loubet-Moundi, in the proceedings of the 7th workshop on Faults Diagnosis and Tolerance in Cryptography (FDTC 2010), IEEE Computer society publisher, August 2010.

 

[CP] Security Evaluation of Asynchronous Circuits” by Jacques J.A. Fournier, Simon Moore, Huiyun Li, Robert Mullins & George Taylor in the Proceedings of the 2003 Workshop on Cryptographic Hardware and Embedded Systems (CHES 2003), Springer-Verlag, September 2003.

 

Integrity & authenticity of ICs (Key words: PUF, Hardware Trojan Detection…)

 

[PAT] “Electronic device having PUF-type identification” by R. Wacquez, J.J.A. Fournier & C. Reita, Published Application EP3246943A1, (priority date : May 2016), published Nov 2017.

 

[J] “On-Chip HT and counterfeits detection” by M. Lecomte, J.J.A. Fournier & P. Maurine, in the IEEE Transactions on Very Large Scale Integration Systems, 2016.

 

[CP] “Granularity and detection capability of an adaptive embedded Hardware Trojan detection system” by M. Lecomte, J.J.A. Fournier & P. Maurine, in the proceedings of HOST 2016, Washington, USA , May 2016.

 

[CP] “New Partitioning Approach for Hardware Trojan Detection Using Side-Channel Measurements” by K. Abdellatif, C. Cornesse, J.J.A. Fournier & B. Robisson, in the proceedings of ARC 2016, Brazil, March 2016.

 

[CP] “On-chip fingerprinting of IC topology for integrity verification” by M. Lecomte, J.J.A. Fournier & P. Maurine, in the proceedings of DATE 2016, Dresden, Germany, March 2016.

 

[CP] “Thoroughly analyzing the use of Ring Oscillators for on-chip Hardware Trojan detection” by M. Lecomte, J.J.A. Fournier & P. Maurine, in the proceedings of the 2015 International Conference on ReConFigurable Computing and FPGAs, Mexico, December 2015.

 

[PAT] “System and method for securing an electronic circuit” by M. Lecomte, J.J.A. Fournier & P. Maurine, Published Application WO/2016/042144, March 2016.

 

[IT] “Extraction of intrinsic structure for Hardware Trojan detection” by M. Lecomte, J.J.A. Fournier & P. Maurine, in Cryptology ePrint Archive, Report 2015/912, http://eprint.iacr.org/,2015.

 

[CP] “SEMBA: A SEM Based Acquisition technique for fast invasive Hardware Trojan detection” by F. Courbon, P. Loubet-Moundi, J.J.A. Fournier & A. Tria, in proceedings of ECCTD’15, Trondheim, Norway, August 2015.

 

[BC] "Physically Unclonable Function: Design of a Silicon Arbiter-PUF on CMOS 65nm", by Jacques J.A. Fournier & Guillaume Reymond, in "Trusted Computing for Embedded Systems", Candaele  Bernard, Soudris Dimitrios, Anagnostopoulos Iraklis (Eds.), pp 135-142, Springer, ISBN 978-3-319-09419-9, November 2014.

 

[CP] A practical framework for assuring authenticity and integrity of hardware components” by C. Rust, H. Bock, V. Brunner, M. Deutschmann, J.J.A. Fournier, J. Hermans & D. Singeelee, in the proceedings of Smart Systems Integration international conference & exhibition (SSI 2014), Vienna, March 2014.

 

[IT] “Imaging techniques for the Detection of Hardware Trojans” by Franck Courbon, Philippe Loubet-Moundi, Jacques Fournier & Assia Tria, presentation made at TRUDEVICE – WG Meetings, Germany, December 2013.

 

[CP] Practical measurements of data path delays for IP authentication & integrity verification by I. Exurville, J. Fournier, J-M. Dutertre, B. Robisson & A. Tria, in the proceedings of the 8th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC’2013), IEEE Xplore, July 2013.

 

Trusted computing & secure systems (Key words: Internet of Things, Trusted Platform Module, Secure tokens, smart grids…)

 

[CP] “Hardware Security Threats Against Bluetooth Mesh Networks” by Alexandre Adomnicai, Laurent Masson & Jacques J.A. Fournier, in the proceedings of the IEEE Conference on Communications and Network Security 2018, Beijing, China, June 2018.

 

[IT] “End-to-end data security for IoT: from a cloud of encryptions to encryption in the cloud” by Anne Canteaut, Sergiu Carpov, Caroline Fontaine, Jacques Fournier, Benjamin Lac, Maria Naya-Plasencia, Renaud Sirdey and Assia Tria, at “Journée Nouvelles Avancées en Sécurité des Systèmes d'Information”, Toulouse (France), January 2018.

 

[IT] “End-to-end data security for IoT: from a cloud of encryptions to encryption in the cloud” by Anne Canteaut, Sergiu Carpov, Caroline Fontaine, Jacques Fournier, Benjamin Lac, Maria Naya-Plasencia, Renaud Sirdey and Assia Tria, at the C&ESAR 2017 Conference, Rennes, France, November 2017.

 

[IT] Short & long term research agenda for IoT security” by J. Fournier, at the Connect Security World 2017, Marseilles, France, September 2017.

 

[IT] “Challenges of the Emerging IoT Security Arena” by J. Fournier and A. Merle, at the Design Automation Conference (DAC 2017), Austin, USA, June 2017.

 

[IT] “Table ronde : Sécurité dans l’Internet des Objets” by J. Fournier, at the Rendez-vous de la Recherche et de l'Enseignement de la Sécurité des Systèmes d'Information (RESSI 2017), Autrans, France, May 2017.

 

[J] “Cahier Technique : Sécuriser les objets connectés” by A. Tria and J. Fournier, in ‘Industrie et Technologies’ (available here), 1er Mars 2017.

 

[IT] “Securing the IoT Jungle” by A. Tria and J. Fournier, at the C&ESAR 2016 Conference, Rennes, France, November 2016.

 

[IT] “How far can we trust our microchips?” by J. Fournier, at the Aero’Nov Connection 2016, Aix-en-Provence, France, May 2016.

 

[IT] “Smart Homes’ security: from theory to practice” by J. Fournier, M. Gallissot, C. Hennebert & K. Zunino, at the ETSI - Internet of Things in the Smart Home workshop, Sophia-Antipolis, France, March 2016.

 

[IT] “Pourquoi sécuriser l’implémentation des algorithmes cryptographiques” by Jacques Fournier, Master Class given at the FIC2016, Lille, France, January 2016.

 

[IT] “End-2-end security for smart grid’s cyber systems” by Jacques Fournier & Sara Tucci, Innovative City 2015, Nice, June 2015.

 

[J] “Security Challenges facing the IoT” by Jacques Fournier, Assia Tria, Florian Pebay & Dominique Noguet, in the Pan European Networks Science & Technology, pp 66-67, Issue 13, December 2014.

 

[CP] A Secure Docking Module for providing trust in Crisis Management Incidents by A.P. Fournaris, D. Hein J. Fournier, G. Reymond & H. Brandl, in the proceedings of the IEEE IES 11th IEEE International Conference on Industrial Informatics (INDIN 2013), July 2013.

 

[J] “Secure Docking Station and its protection against hardware attacks” by A.P. Fournaris, J. Fournier, D. Hein & G. Reymond, in the journal “Technical Sciences”, University of Warmia and Mazury in Olsztyn, pp 123-138, UWM publisher, Poland, September 2012.

 

[CP] “TISPHANIE, bringing the truth about the security of mobile phones” by Jacques Fournier & Anthony Ferrari, in the Proceedings of the e-Smart 2010, September 2010.

 

[CP] “USB Tokens as Security Enabler for Mobility Solutions” by Jacques Fournier & Gérald Maunier in the Proceedings of the e-Smart 09, September 2009.

 

[PAT] “Security token for securely executing an application on a host computer” by J. Fournier, P. Girard & P. Proust. Application N° EP 10305516.6 (17/05/2010); Publication N° 2388728 A1 (23/11/2011).

 

[PAT] “Software security module using the encryption of the Hash of a password concatenated with a seed” by J. Fournier. Application N° EP 09305657.0 (07/07/2009); Publication N° EP 2285042 A1 (16/02/2011), WO/2011/003722 (13/01/2011).

 

[PAT] “Making the location of a remote code secure through the recipient’s imprint” by J. Fournier, L. Gauteron, F. Imoucha & V. Charpeignet. Application N° EP 09305649.7 (06/07/2009); Publication N° EP 2273407 A1 (12/01/2011), WO/2011/003721 (13/01/2011).

 

[PAT] “Method for remotely validating executable code” by J. Fournier & P. Girard. Application N° PCT/EP2010/058673 (18/06/2010); Publication N° WO/2011/000722 (06/01/2011).

 

[PAT] “Method of dynamic protection of data during the execution of a software code in intermediate language in a digital apparatus” de B. Gonzalvo & J. Fournier. Published Applications: US2009328231, December 2009.

 

[PAT] “Un procédé de protection dynamique des données lors de l’exécution d’un code logiciel en langage intermédiaire dans un appareil portatif” de J. Fournier & B. Gonzalvo. Published Applications: EP1881404 / WO2008009697, July 2006.

 

[PAT] “Transmission sécurisée de données entre deux modules / Secure data transmission between two modules” d’O. Benoit, E. Brier, J. Fournier, P. Moitrel & P. Proust. Patents Delivered: FR2855286(France), US7856099(US). Published Applications: EP1629625(A1) / CN1792059(A) / US2007055868(A1) / WO2004105304(A1), May 2003.

 

Hardware designs for cryptography & security (Key words: Hardware countermeasures, vector processing, asynchronous logic…)

 

[CP] “Dynamic encoding, a lightweight combined countermeasure against hardware attacks” by M. Montoya, S. Bacles Min, A. Molnos & J. Fournier in the proceedings of Euromicro DSD Confence 2020, Portoroz, Slovenia, August 26-28, 2020.

 

[CP] “Recommendations for a radically secure ISA” by M. Escouteloup, R. Lashermes, J. Fournier & J-L. Lanet, presented at the Fourth Workshop on Computer Architecture Research with RISC-V (CARRV 2020), colocated with ISCA 2020      (available here), May 29th, 2020.

 

[CP] “Adaptive Masking: a Dynamic Trade-off between Energy Consumption and Hardware Security” by M. Montoya, T. Hiscock, S. Bacles Min, A. Molnos & J. Fournier in the proceedings of IEEE ICCD 2019, Abu Dhabi, United Arab Emirates, , November 17-20, 2019.

 

[CP] “Energy-efficient Masking of the Trivium Stream Cipher” by M. Montoya, T. Hiscock, S. Bacles Min, A. Molnos & J. Fournier in the proceedings of the 25th IEEE International Conference on Electronics Circuits and Systems (ICECS 2018), Bordeaux, France, December 2018.

 

[CP] “SWARD: A Secure WAke-up RaDio against Denial-of-Service on IoT devices” by M. Montoya, S. Bacles Min, A. Molnos & J. Fournier in the proceedings of the 11th ACM Conference on Security and Privacy in Wireless and Mobile Networks (WiSec 2018), Stokhlom, Sweden, June 2018.

 

[PAT] Registre à décalage protégé contre les attaques physiques” by M. Montoya, S. Bacles Min, A. Molnos & J. Fournier filed on July 2018.

 

[CP] “Lightweight and secure scheme to mitigate Denial-of-Sleep on wake-up radios for IoT devices” by M. Montoya, S. Bacles Min, A. Molnos & Jacques Fournier, poster presented at the DAC 2018, San Francisco (USA), June 2018.

 

[PAT] Dispositif d’émission / réception à radio de réveil résistant aux attaques par déni de sommeil by M. Montoya, S. Bacles Min, A. Molnos & J. Fournier filed on August 2017.

 

[CP] “A Side-Channel and Fault Attack Resistant AES circuit working on duplicated complemented values” by Marion Doulcier-Verdier, Jean-Max Dutertre, Jacques Fournier, Jean-Baptiste Rigaud, Bruno Robisson & Assia Tria, in Solid State Circuits Conference — Digest of technical papers, 2011 (ISSCC 2011), page 15.6,  IEEE International, February 2011.

 

[THESIS] Vector microprocessors for cryptography” by Jacques J.A. Fournier, University of Cambridge, Computer Laboratory Technical Report UCAM-CL-TR-701, October 2007.

 

[CP] “Hardware-Software Co-design of a Vector Co-processor for Public Key Cryptography” by Jacques Fournier & Simon Moore in the Proceedings of the 9th EuroMicro Conference on Digital System Design, Architectures, Methods & Tools (DSD 2006), IEEE Computer Society publisher, August 2006.

 

[CP] “Implementing Cryptography on TFT Technology for Secure Display Applications” by Petros Oikonomakos, Jacques Fournier & Simon Moore in the LNCS Proceedings of the 7th Smart Card Research and Advanced Applications IFIP Conference (CARDIS’06), pp 32-47, April 2006.

 

[CP] “A vector approach to Cryptography Implementation” by Jacques J. Fournier & Simon Moore in the LNCS Proceedings of the 1st International Conference on Digital Rights Management Technologies Issues Challenges and Systems (DRMtics 2005), November 2005.

 

[J]La carte à puce et les circuits asynchrones” de Jacques Fournier et Simon W. Moore, numéro spécial de la ‘Revue de l’Electricité et de l’Electronique et des Technologies de l’Information et de la Communication’, Août 2004.

 

[J]Balanced Self-Checking Asynchronous Logic for Smart Card Applications” by S.W. Moore, Ross Anderson, Robert Mullins, George Taylor & Jacques Fournier in the Journal of Microprocessors and Microsystems, IEEE Special Issue on asynchronous circuits, October 2003.

 

[IT]Reducing smart card information leakage” by Jacques Fournier in special promotion of the ‘Technology Marketplace’ of CORDIS (the European Commission's official information service for Research & Development), available here, 2003.

 

[IT] “Secure Architectures: Requirements and Assessment” by Jacques Fournier, invited talk given at the 1st International Workshop on Embedded Reconfigurable Architectures for Applied Cryptography (CryptArchi 2003), January 2003.

 

 

Collaborative Projects

 

MOBITRUST: Mobile Trust  (EUREKA CATRENE 2013) : 2014-2017.

Keywords : Privacy preserving technologies, secure memories, forensics…

 

HINT: Holistic Approaches for Integrity of ICT systems (EU FP7 – 317930) : 2012-2015.

Keywords : Trojan detection, embedded system integrity, side channel leakages, PUFs…

 

TOISE: Trusted Computing for European Embedded Systems (EU ENIAC Joint Undertaking) : 2011-2013.

Keywords : trusted computing, smart grids, wireless sensor networks, secure detachable modules, PUF, VHDR, side channel attacks, fault attacks…

 

ECLIPSES: Elliptic Curve Leakage-Immune Processing for Secure Embedded Systems (French ANR – SCS labelling) : 2009-2012.

Keywords : elliptic curve cryptography, pairings, hardware accelerators, side channel attacks, fault attacks…

 

SECRICOM: Seamless Communication for Crisis Management (EU FP7 – 218123) : 2008-2012. 

Keywords : crisis management, secure communication networks, local device attestation, network monitoring…

{Video on main achievements here}.

 

TISPHANIE: Technologies en Investigations Sécuritaires pour téléphones et appareils numériques mobiles (French FUI Pôle System@tic) : 2009-2011.

Keywords : Mobile phones’ security, side channel attacks, secure hypervisors, PMR, methodology evaluation…

 

DURACELL: Durcissement aux Attaques par fautes de Cellules pour circuits sécuritaires (French RNRT) :.

Keywords : fault resistant designs, laser attacks, fault attacks, countermeasures…

 

InspireD: Integrated Secure Platform for Interactive Personal Devices (EU FP6) : 2004-2007.

Keywords : trusted computing, e-services, mobile devices, smart cards, side channel and fault attacks, trusted personal devices…

 

G3CARD: Generation 3 smart CARD (EU FP5 IST-1999-13515) :1999-2003.

Keywords : asynchronous circuits, smart cards, side channel attacks, fault attacks…

 

 

Supervisions

 

PHDs (ongoing)

o   Mathieu ESCOUTELOUP (since Oct 2018) : “ Sécurité des mirco-architectures ”, thèse Inria-DGA, directors :Jean-Louis Lanet (Inria) & Jacques Fournier.

 

PHDs (completed)

o   Maxime MONTOYA (Oct 2016 – Dec 2019) : “ Sécurité adaptative et énergétiquement efficace dans l’Internet des Objets”, director: Jacques Fournier (EMSE).

o   Antoine LOISEAU (July 2016 – Nov 2019) :Lightweight and secure Elliptic Curves Cryptography for the IoT”, directors : Jacques Fournier (EMSE) & Assia Tria (EMSE) – now researcher at the CEA Leti.

o   Alexandre ADOMNICAI (March 2016 – July 2019) :Secure implementation & integration of LWC for the IoT”, directors : Jacques Fournier (EMSE) & Assia Tria (EMSE), Cifre with Trusted Objects – now post-doctoral researcher at the Nanyang Technological University (NTU), Singapore.

o   Benjamin LAC (Sept 2015 – Oct 2018) : “Side channel resistant & fault resilient Light Weight Cryptography (LWC) for IoT infrastructures”, directors : Jacques Fournier (EMSE) & Anne Canteaut (UPMC) – now research-engineer at Invia.

o   Damien JAUVART (Sept 2014 – Sept 2017) : Protecting Pairing algorithms against physical attacks”, director : Louis Goubin (UVSQ) – now researcher at Aix-Marseille University.

o   Maxime LECOMTE (Oct 2013 – Oct 2016) : “Système embarqué de mesure de la tension pour la détection de contrefaçons et de chevaux de Troie matériels”, director: Philippe Maurine (ENSMSE/LIRMM) – now researcher at CEA Leti.

o   Franck COURBON (Sept 2012 – Sept 2015) : “Rétro conception matérielle partielle appliquée à l’injection ciblée de fautes laser et à la détection efficace de chevaux de Troie matériels”, director : Assia Tria (ENSMSE) – now researcher at University of Cambridge.

o   Ronan LASHERMES (Sept 2011 – Sept 2014) :On the security of pairing implementations”, director: Louis Goubin (UVSQ) – now researcher at Inria.

 

 

MASTERS’ INTERNSHIPS (completed)

o   Marc BEUNARDEAU (Mar – Aug 2015) :Lightweight Cryptography and physical attacks”, now PhD student at Ingenico.

o   Romain FERRAND (Mar – Sept 2013) : “Caractérisation sécuritaire d'un composant électronique en FD-SOI”.

o   Marie PAINDAVOINE (Mar – Sept 2013) : “Mise en œuvre d’attaques physiques sur les algorithmes cryptographiques de Couplage (Pairing)”, completed her PhD at Orange Labs.

o   Ingrid EXURVILLE (Mar – Sept 2012) :Devising a method for hardware Trojan detection on an AES circuit”, completed her PhD in September 2015.

o   Olivier VALLIER (AugJul 2012) : “Etude de faisabilité: récupération physique et de données dans un téléphone portable”, now engineer.

o   Ronan LASHERMES (Mar – Sept 2011) :VHDL design of the decryption mode of a secure cryptographic coprocessor and study of countermeasures against a clock glitch attack, completed his PhD in September 2014..

o   Guillaume EGEA (Mar – Sept 2011) : “Caractérisation de sondes électromagnétiques dédiées à l’évaluation sécuritaire des circuits intégrés”, now working for Alten (Paris).

o   Cyril ROSCIAN (Mar – Sept 2010) :Functional Evolution and Security Study of an AES Cryptographic co-processor”, completed his PhD in October 2013.

 

 

Other research-related activities

 

Program Committee memberships

o   Transaction on CHES – CHES 2018.

o   Connect Security World 2017 & 2018.

o   21st Euromicro Conference on Digital System Design (DSD 2018), special session on "Architecture and Hardware for Security Applications (AHSA)"

o   20th Euromicro Conference on Digital System Design (DSD 2017), special session on "Architecture and Hardware for Security Applications (AHSA)"

o   4th Workshop on Cryptography and Security in Computing Systems – CS2 2017.

o   3rd Workshop on Cryptography and Security in Computing Systems – CS2 2016.

o   2nd Workshop on Cryptography and Security in Computing Systems – CS2 2015.

 

Contact

 

Minatec Campus, 17 Rue des Martyrs, 38054 Grenoble Cédex, France.

 

E-MAIL : firstname.lastname at cea dot fr